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M5450 M5451
LED DISPLAY DRIVERS
FEATURES SUMMARY M5450 34 OUTPUTS/15mA SINK

Figure 1. Packages
M5451 35 OUTPUTS/15mA SINK CURRENT GENERATOR OUTPUTS (NO EXTERNAL RESISTORS REQUIRED) CONTINUOUS BRIGHTNESS CONTROL SERIAL DATA INPUT ENABLE (ON M5450) WIDE SUPPLY VOLTAGE OPERATION TTL COMPATIBILITY
40

1
PDIP40 (Plastic Package)
Application Examples: MICROPROCESSOR DISPLAYS

INDUSTRIAL CONTROL INDICATOR RELAY DRIVER INSTRUMENTATION READOUTS
PLCC44 (Plastic Chip Carrier)
DESCRIPTION The M5450 and M5451 are monolithic MOS integrated circuits produced with an N-channel silicon gate technology. They are available in 40-pin dual in-line plastic packages. A single pin controls the LED display brightness by setting a reference current through a variable resistor connected to VDD or to a separate supply of 13.2V maximum.
REV. 2 April 2004 1/12
M5450, M5451
Figure 2. Pin Connection
OUTPUT BIT 14
OUTPUT BIT 15
OUTPUT BIT 16
OUTPUT BIT 17
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20 42
V SS OUTPUT BIT 17 OUTPUT BIT 16 OUTPUT BIT 15 OUTPUT BIT 14 OUTPUT BIT 13 OUTPUT BIT 12 OUTPUT BIT 11 OUTPUT BIT 10 OUTPUT BIT 9 OUTPUT BIT 8 OUTPUT BIT 7 OUTPUT BIT 6 OUTPUT BIT 5 OUTPUT BIT 4 OUTPUT BIT 3 OUTPUT BIT 2 OUTPUT BIT 1 BRIGHTNESS CONTROL V DD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
OUTPUT BIT 18 OUTPUT BIT 19 OUTPUT BIT 20 OUTPUT BIT 21 OUTPUT BIT 22 OUTPUT BIT 23 OUTPUT BIT 24 OUTPUT BIT 25 OUTPUT BIT 26 OUTPUT BIT 27 OUTPUT BIT 28 OUTPUT BIT 29 OUTPUT BIT 30 OUTPUT BIT 31 OUTPUT BIT 32 OUTPUT BIT 33 OUTPUT BIT 34 DATA ENABLE FOR M5450 OUTPUT BIT 35 FOR M5451 DATA IN CLOCK IN
N.C
44
43
41
OUTPUT BIT 21
VSS
OUTPUT BIT 13 OUTPUT BIT 12 OUTPUT BIT 11 OUTPUT BIT 10 OUTPUT BIT 9 N.C. OUTPUT BIT 8 OUTPUT BIT 7 OUTPUT BIT 6 OUTPUT BIT 5 OUTPUT BIT 4
40
6
5
4
3
2
1
OUTPUT BIT 22
7 8 9 10
11 12 13 14 15 16 17
39 38 37 36
35 34 33 32 31 30 29
OUTPUT BIT 23 OUTPUT BIT 24 OUTPUT BIT 25 OUTPUT BIT 26 OUTPUT BIT 27 N.C. OUTPUT BIT 28 OUTPUT BIT 29 OUTPUT BIT 30 OUTPUT BIT 31 OUTPUT BIT 32
18
19
21
22
23
24
25
26
20
27 OUTPUT BIT 34
BRIGHTNESS CONTROL
Figure 3. Block Diagram
VDD BRIGTHNESS CONTROL 100k OUTPUT BIT 34 20 24 OUTPUT BIT 1 18
19
35 OUTPUT BUFFERS
LOAD
DATA ENABLE (M5450) OUTPUT35 (5451) 35 LATCHES
23
SERIAL DATA
22
35-BIT SHIFT REGISTER RESET
CLOCK
21
1
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DATA IN OUTPUT BIT 35
OUTPUT BIT 33
OUTPUT BIT 3
OUTPUT BIT 1
OUTPUT BIT 2
N.C
CLOCK IN
VDD
28
M5450, M5451
Table 1. Absolute Maximum Ratings
Symbol VDD VI VO(off) IO PTOT Tj TOP TSTG Supply Voltage Input Voltage Off State Output Voltage Output Sink Current Total Package Power Dissipation at 25C Total Package Power Dissipation at 85C Junction Temperature Operating Temperature Range Storage Temperature Range Parameter Value - 0.3 to 15 - 0.3 to 15 15 40 1 560 150 - 25 to 85 - 65 to 150 Unit V V V mA W mW C C C
Note: Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
FUNCTIONAL DESCRIPTION Both the M5450 and the M5451 are specially designed to operate 4 or 5-digit alphanumeric displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Using a format of a leading "1" followed by the 35 data bits allows data transfer without an additional load signal. The 35 data bits are latched after the 36th bit is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. Display brightness is determined by control of the output current LED displays. A 1nF capacitor should be connected to brightness control, pin 19, to prevent possible oscillations. A block diagram is shown in Figure 3. For the M5450 a DATA ENABLE is used instead of the 35th output. The DATA ENABLE input is a metal option for the M5450. The output current is typically 20 times greater than the current into pin 19, which is set by an external variable resistor. There is an internal limiting resistor of 400W nominal value. Figure 4 shows the input data format. A start bit of logical "1" precedes the 35 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 35 bits of the shift registers into the latches. At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static
master-slave configurations. There is no clear for the master portion of the first shift register, thus allowing continuous operation. There must be a complete set of 36 clocks or the shift registers will not clear. When power is first applied to the chip an internal power ON reset signal is generated which resets all registers and all latches. The START bit and the first clock return the chip to its normal operation. Bit 1 is the first bit following the start bit and it will appear on Pin 18. A logical "1" at the input will turn on the appropriate LED. Figure 5 shows the timing relationship between Data, Clock and DATA ENABLE. A max clock frequency of 0.5MHz is assumed. For applications where a lesser number of outputs are used, it is possible to either increase the current per output or operate the part at higher than 1V VOUT. The following equation can be used for calculations. Tj = [(VOUT) (ILED) (No. of segments) + (VDD x 7mA)] (124C/W) + Tamb where : Tj = junction temperature (150C max) VOUT = the voltage at the LED driver outputs ILED = the LED current 124C/W = thermal coefficient of the package Tamb = ambient temperature The above equation was used to plot Figure 6, Figure 7 and Figure 8.
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M5450, M5451
Table 2. Static Electrical Characteristics (Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified)
Symbol VDD IDD VI Parameter Supply Voltage Supply Current Input Voltage Logical "0" Level Logical "1" Level IB VB VO(off) IO Brightness Input Current (note 2) Brightness Input Voltage (pin 19) Input Current = 750A, Tamb = 25C Off State Out. Voltage Out. Sink Current (note 3) Segment OFF Segment ON VO = 3V VO = 1V (note 4) Brightness In. = 0A Brightness In. = 100 Brightness In. = 750A fclock IO
Note: 1. 2. 3. 4.
Test Conditions VDD = 13.2V 10A Input Bias 4.75 VDD 5.25 VDD > 5.25
Min. 4.75 - 0.3 2.2 VDD - 2 0 3
Typ.
Max. 13.2 7 0.8 VDD VDD 0.75 4.3 13.2 10
Unit V mA V V V mA V V A A mA mA MHz %
0
10 27 15 4 25 0.5 20
2
12 0
Input Clock Frequency Output Matching (note 1)
Output matching is calculated as the percent variation from I MAX + IMIN/2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another. Absolute maximum for each output should be limited to 40mA. The VO voltage should be regulated by the user. See Figure 7 and Figure 8 for allowable VO versus IO operation.
Figure 4. Input Data Format
1 CLOCK START DATA BIT 1 BIT 34 BIT 35 36
LOAD (INTERNAL)
RESET (INTERNAL)
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M5450, M5451
Figure 5. Figure 6.
Ptot (W) 15mA/segment 34 segments VO = 1V
1.0
CLOCK
0.8
DATA 300ns (min.)
0.6 0.4 0.2
100ns (min.)
SAFE OPERATING AREA T amb (C)
DATA ENABLE
0
20
40
60
80
100
Figure 7.
VO (V)
Figure 8.
I0 (mA)
3.2
105
2.8
2.4 2.0
20 segments 30 segments 34 segments
85
65
Tamb = 85C IO (max.) = 40mA
VO = 1V VO = 1.5V VO = 2V N Segm.
1.6
1.2 0.8
0.4
45
Tamb = 85C
Tj = 150C (max.)
4 8 12 16 20
ILED (mA)
25
5
0
24
28
32
0
4
8
12
16 20
24
28 32
36 40
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M5450, M5451
TYPICAL APPLICATIONS Figure 9. Basic Electronically Tuned Radio Or Tv System
AM FM
34 SEGMENTS
M5450 DISPLAY DRIVER
KEYBOARD
ELECTRONIC TUNING CONTROLLER
PLL SYNTHESIZER
STATION DETEC. ETC.
Figure 10. Duplexing 8 Digits With One M5450
VDD VLED VLED VDD
.
.
.
.
.
.
.
.
9 16
28 40
32 39
24 31
M5450
18 CLOCK IN DATA IN
BRIGHTNESS CONTROL VDD
21
22
19
20
1
23
17
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M5450, M5451
POWER DISSIPATION OF THE IC The power dissipation of the IC can be limited using different configurations. Figure 11- In the application R must be chosen taking into account the worst operating conditions. Figure 11.
+VC
+VC
The total power dissipation of the IC depends, in a first approximation, only on the number of segments activated. Figure 12.
R
ID VD
VOUT
R is determined by the maximum number of segments activated
V -V -V C DMAX OMIN R = ---------------------------------------------------------------N L MAX D
Figure 13 - In this configuration VOUT + VD is constant. The total power dissipation of the IC depends only on the number of segments activated. Figure 13.
+VC
The worst case condition for the device is when roughly half of the maximum number of segments are activated. It must be checked that the total power dissipation does not exceed the absolute maximum ratings of the device. In critical cases more resistors can be used in conjunction with groups of segments. In this case the current variation in the single resistor is reduced and Ptot limited. Figure 12 - In this configuration the drop on the serial connected diodes is quite stable if the diodes are properly chosen.
VOUT +VD
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M5450, M5451
PART NUMBERING Table 3. Order Codes
Part Number M5450B7/M5451B7 M5451Q Package PDIP40 PLCC44 Temperature Range -25 to 85 C -25 to 85 C
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M5450, M5451
PACKAGE MECHANICAL Table 4. PDIP40 - Mechanical Data
millimeters Symbol Typ a1 b b1 b2 D E e e3 F i L 4.445 3.3 15.2 2.54 48.26 14.1 0.175 0.130 0.23 1.27 52.58 16.68 0.598 0.100 1.900 0.555 Min 0.63 0.45 0.31 0.009 0.050 2.070 0.657 Max Typ Min 0.025 0.018 0.012 Max inches
Figure 14. PDIP40 - Package Dimensions
a1
L
I
b1 b b2 e3 e E
D
40
21
1
20
Note: Drawing is not to scale
F
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M5450, M5451
Table 5. PLCC44 - Mechanical Data
millimeters Symbol Typ A B C D d1 d2 E e e3 F F1 G M M1 1.16 1.14 14.99 1.27 12.7 0.46 0.71 0.101 0.046 0.045 17.4 16.51 3.65 4.2 2.59 0.68 16 0.590 0.050 0.500 0.018 0.028 0.004 Min Max 17.65 16.65 3.7 4.57 2.74 Typ 0.685 0.650 0.144 0.165 0.102 0.027 0.630 Min Max 0.695 0.656 0.146 0.180 0.108 inches
Figure 15. PLCC44 - Package Dimensions
B M1
6 2 1 44 39
C M
M1
E
e3
17 18 28
29
A G (Seating Plane Coplanarity)
F1
e
F
d2 d1 D
Note: Drawing is not to scale.
10/12
M
7
38
M5450, M5451
REVISION HISTORY Table 6. Revision History
Date September-1993 14-Mar-2004 Revision 1 2 First Issue Stylesheet update. No content change. Description of Changes
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M5450, M5451
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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